Audio is not get

Question

I am interfacing a TLV320AIC3204 codec EVM with an nRF54L15 board using I2S. 
 The codec EVM default configuration is working correctly. I verified audio on the EVM side. 
 Current clock configuration:

MCLK = 12 MHz

BCLK = 3 MHz

LRCK = 48 kHz

I am using clocks generated from the codec EVM and connecting them to the nRF54L15 board. The nRF54L15 is configured as I2S slave. 
 Issue: 
 I am not receiving ADC audio data on the nRF54L15 side. ADC values remain zero. 
 I am using IN3L microphone input on the codec. Codec initialization completes successfully and clocks are present. However, nRF54L15 does not receive audio samples. 
 Current observations:

Codec EVM default condition works

MCLK/BCLK/LRCK are measured and present

ADC path initialization completes

nRF54L15 I2S RX does not receive valid audio data

ADC values remain zero

Could anyone suggest what should be checked on the Nordic side (I2S configuration, pin mapping, clock slave configuration, RX trigger sequence, or other nRF54L15-specific requirements)?

const codec_register CODEC_DEF_REG_DATA [] = { 
 
 // ---- Page 0: Reset + Clock ---- 
 { 0 , 0x00 }, // Select Page 0 
 { 1 , 0x01 }, // Software reset (wait 1ms after) 
 
 { 0 , 0x00 }, // Select Page 0 
 { 4 , 0x03 }, // PLL_CLKIN = MCLK, CODEC_CLKIN = PLL 
 { 5 , 0x91 }, // PLL power up, P=1, R=1 
 { 6 , 0x07 }, // J=7 
 { 7 , 0x00 }, // D MSB 
 { 8 , 0x90 }, // D LSB (D=0.144 → Fout=12MHz×7.144/2/2 = ~48kHz path) 
 
 { 27 , 0x0C }, // I2S, 16-bit, codec slave 
 
 { 11 , 0x82 }, // NDAC=2, powered up 
 { 12 , 0x87 }, // MDAC=7, powered up 
 { 13 , 0x00 }, // DOSR MSB 
 { 14 , 0x80 }, // DOSR=128 
 { 18 , 0x82 }, // NADC=2, powered up 
 { 19 , 0x87 }, // MADC=7, powered up 
 { 20 , 0x80 }, // AOSR=128 
 
 { 29 , 0x01 }, // BDIV_CLKIN = DAC_CLK 
 { 30 , 0x82 }, // BCLK N=2, powered up 
 
 // DAC & ADC processing blocks 
 { 60 , 0x08 }, // DAC PRB_P8 
 { 61 , 0x01 }, // ADC PRB_R1 
 
 // ---- Page 1: Analog power + MIC routing ---- 
 { 0 , 0x01 }, // Select Page 1 
 { 1 , 0x08 }, // Disable weak AVDD 
 { 2 , 0x00 }, // Enable Master Analog Power Control 
 
 { 10 , 0x00 }, // Common mode = 0.9V 
 
 { 71 , 0x32 }, // MicPGA startup delay = 3.1ms 
 { 123 , 0x01 }, // REF charging time = 40ms 
 
 { 51 , 0x68 }, // MICBIAS: powered up (D6=1), 2.5V (D5-D4=10), from AVDD 
 
 // Route IN3L → LEFT_P at 20kΩ (D3-D2 = 10 = 0x08) 
 { 52 , 0x08 }, // IN3L to Left MICPGA P-terminal, 20kΩ 
 
 // Route CM → LEFT_M at 20kΩ via CM1L (D7-D6 = 10 = 0x80) 
 { 54 , 0x80 }, 
 
 { 59 , 0x77 }, // Left MICPGA: unmuted (D7=0), gain=6dB (0dB channel gain with 20kΩ) 
 { 60 , 0x80 }, // Right MICPGA: muted 
 
 // ---- Page 0: Power up ADC ---- 
 { 0 , 0x00 }, // Select Page 0 
 { 81 , 0xC0 }, // Power up Left + Right ADC 
 { 82 , 0x00 }, // Unmute ADC 
 { 83 , 0x28 }, // Left ADC digital volume +12.5dB 
 { 84 , 0x1B }, // Right ADC digital volume +13.5dB 
 }; 
 
 Thank you.