Hi:
use nrf54l15 and ncs v3.1.1.
The CS-PIN remained low during measurement.
I am unable to control CS PIN through DPPI.
Here is the source code:
Hi:
use nrf54l15 and ncs v3.1.1.
The CS-PIN remained low during measurement.
I am unable to control CS PIN through DPPI.
Here is the source code:
Hello,
I don't immediately see what is wrong with the CS handling in your code, but is there a reason for not letting the SPI peripheral control the CS signal as I did in my sample app here: https://github.com/vidarbe/ncs-samples/tree/add_dppi_version/sensor_hub_with_dppi_lm20?
Best regards,
Vidar
EDIT: a coworker pointed out that the GPIOTE task config has the polarity set to NRF_GPIOTE_POLARITY_NONE. This should be sett to NRF_GPIOTE_POLARITY_TOGGLE if you want the signal to be asserted and de-asserted by a single event.
Hi:
Thanks for your help!
After changing NRF_GPOTE-POLARITY_TOGGLE to CS, there is a level change, but the waveform is incorrect. The frequency of CLK is sometimes 6.67MHz and sometimes 10MHz.
It's strange that there was a pull up in the middle of the CS pin.
Hi:
Thanks for your help!
After changing NRF_GPOTE-POLARITY_TOGGLE to CS, there is a level change, but the waveform is incorrect. The frequency of CLK is sometimes 6.67MHz and sometimes 10MHz.
It's strange that there was a pull up in the middle of the CS pin.
The tested board is NRF54L15DK.
It seems like the logic analyser is not able to capture the signal correctly. Perhaps the sampling rate is not sufficient? For testing purposes, I suggest you lower the SPIM frequency below 1MHz to see if this improves the clock signal.