Hi All, In the NRF54L15 SoC, the main ARM core and the co-processor RISC core share the same set of peripherals even though both the cores can have separate sections of RAM and Flash memories.
So, can the two cores have separate memory mapping for all the peripherals in the SoC so that failure in accessing the peripherals by one core do not affect peripheral access by the other core ?
The development setup iam planning to use are:
1. NRF54L15 based Off-the-shelf module
2. WIndows 11 host development PC
3. Bare-metal implementation on the SoC module
Let me know any more inputs required. Thanks in advance !