Operating I2S master with Sensibel 24-bit microphones

[Einar Mestad]

Hi, 
We want to use Sensibel microphones in a project with nfr9151, and it will be used to sample one microphone (mono) with 24bit data. This microphone seems to require 32 clock cycles on each channel (L/R). MSB is transmitter first, meaning that the last 8 bit is tristated and should not be used. 

It seems that the nfr has maximum CONFIG.SWIDTH = 24, and from what i read it is not possible to get the 8 extra clock cycles needed to configure this correct. 
From my understanding of the configuration options in I2S — Inter-IC sound interface • nRF9151 Product Specification • Technical Documentation it is possible to set 24-bit data, but not configure it to match this (and many other) microphones.

Any suggestions to how we can get this to work?

[Einar Mestad]

Would it be possible to define the with to 16 bit and then use a frequency divider outside of the nrf for the left/right selector? We would then need to configure the 16-bit to have 2x frequency to get the same output frequency. And data would need to be converted from two 16-bit words to one 32-bit word.
Issue 1: Will data stored be placed in two different buffers, one 16-bit for left channel, one 16-bit for right channel. (Only 8 bits will be valid). That means that we need to re-arrange the output after the EasyDMA interrrupt.

Issue 2: The clock divider may add a delay in that may lead to timing or synchronization issues.

[Kenneth]

Hello,

If the I2S operate in Master mode what you ask for is not possible.

If the I2S operate in Slave mode this should be possible, please see the following snippets from the I2S chapter:

"The CONFIG.SWIDTH register primarily defines the sample width of the data written to memory. In master mode, it then also sets the amount of bits per frame. In Slave mode it controls padding/trimming if required. Left, right, transmitted, and received samples always have the same width. The CONFIG.FORMAT register specifies the position of the data frames with respect to the LRCK edges in both Master and Slave modes."

"In slave mode, however, the sample width does not need to equal the frame size. This means you might have extra or fewer SCK pulses per half-frame than what the sample width specified in CONFIG.SWIDTH requires."

From: https://docs.nordicsemi.com/r/bundle/ps_nrf9151/page/i2s.html?section=concept_z2v_24y_vr 

Kenneth