Ready interrupt in SPI RAW master (Serialization)

[yc38]

Hi,

I would like to use SPI raw master library (used on application chip in serialization examples) in my own application.

First, to understand well SPI raw implementation and verify signals I set up this configuration :

• 1 nrf51422 (nRF51-DK board) used as SPI raw master, flash with SPI serialization application chip example “ble_app_hrs_s110_spi_pca10028” (SDK10.0.0)

connected to

• my own microcontroller used as SPI raw slave

---

If I understand well SPI raw protocol, the /RDY signal controlled by slave could delay data transmission from master if it is disable during transfer (see figure1 in "SPI RAW protocol" chapter in SDKv10.0.0).

I wonder about this operation because when I try to disable /RDY line (low to high transition on my microcontroller) during master transmission, the master (nrf51422) react at this interrupt only after end of data transfer occured.

This figure shows an example :

The GPIOTE line represents progress (in/out) of the code in "GPIOTE_IRQHandler"

In this case the contribution of the /RDY signal is really poor! (because despite the /RDY signal is disabled master continuous transmission).

• Is it something that has already been notify by Nordic people or other developers?

• Why priority level interrupts seem to produce a different working as described in the SDK documentation (see chapter "SPI RAW protocol" in SDK documentation)?

Thanks

[Ole Bauck]

Sorry for the late answer. It does not make sense that you are not going into the GPIOTE_IRQHandler before after the SPI transaction is done. The SPI driver is set up in non-blocking mode with priority level APP_PRIORITY_LOW, so between each byte it should go to another interrupt or to main context. If GPIOTE interrupt is APP_PRIORITY_HIGH the SPI should not run before the GPIOTE interrupt if a GPIOTE interrupt is pending, which it should be from the moment READY signal change level.

Have you figured out what was wrong? I cannot help you with no further information.