Questions on nRF54LM20-CAAA (CSP61) hardware design

[zhanxy]

Hello Nordic team,

We are reviewing our nRF54LM20-CAAA (CSP61) hardware design and would appreciate your clarification on several power and RF related points.

1. DECRF related network
   In the reference design, L5 = 1.0 nH is placed between DECRF and DECA, and C8 = 1.0 pF is connected across the two nodes.
   Could you please clarify:
   • What are the specific purposes of the 1.0 nH inductor and the 1.0 pF capacitor?
   • For the CSP61/CAAA variant, are these mandatory fixed values, or are they intended as layout/board-dependent tuning components?
   • If tuning is allowed, what should be optimized when adjusting them: RF performance, supply noise isolation, regulator stability, or something else?
2. C7 marked as NC/DNP in the reference design
   In the same network, C7 is currently marked as NC/DNP.
   Could you please clarify:
   • What is the intended purpose of reserving C7?
   • Under what conditions should C7 be populated?
   • If it should be populated, what value range or selection criteria do you recommend?
3. Power-up / power-down timing of VDD, VBUS, and nRESET
   Could you please provide or confirm:
   • The power-up and power-down timing diagram for VDD, VBUS, and nRESET;
   • Any mandatory sequencing constraints, minimum delay requirements, or ordering requirements;
   • Any special considerations when VBUS is present before VDD, or when VBUS comes up after VDD.
4. Main DC/DC related to DCC/DECD
   For the main DC/DC regulator associated with DCC/DECD, could you please clarify:
   • What is the actual peak current? If possible, we would like to know both the peak inductor current and the peak load current.
   • What is the typical switching frequency?
   • Is the 4.7 uH inductor in the reference design mandatory, or can it be adjusted?
   • If it can be adjusted, what is the supported inductance range, and what are the key selection criteria such as saturation current, DCR, ripple, efficiency, and transient performance?

Thank you.