Trying to access documentation from https://www.nordicsemi.com/Products/Development-hardware/nRF54L15-DK/Hardware-files?lang=en#infotabs to get pin mapping as i am facing issues GETTING 404 error while accessing documentation page for last 2 weeks now. I am using NRF54L15-DK with 1.28 round display SPI configuration mentioned below. I am not able to get Simple test displayed on the screen, i am not sure if any ports are getting conflict have document my views in devicetree based on reading of DK dtsi file ,
BOOT SPI TRANSFER IS LOOKING GOOD in boot log details below. I require help and support on resolving this as product launch is getting delayed , any support will be really helpful.
Any suggestions / other diagnostics which can be done to resolve this ?
Should i disconnect the QSPI flash pins ??
Dev KIT: PCA101506 0.9.3 2025.19
VDDIO: Set to 3.3V in Board configurator and Display is connected to it.
i am not getting any error in build and flash
I am use the following pins
1. SPI pin Configurations
P2.06=SCK ; SPI CLOCK -> Mapped to SCL in Display Module
P2.08=MOSI ; display writes run in a - > Connected to SDA in Display Module
P2.09=MISO ; Not used by Display, used by Other SPI device. (Not used)
P2.10= CS0 : Different SPI Device (Not connected)
P2.03= CS1 :GC9A01 (via MIPI-DBI in device tree) - Connected to CS in Display module
P2.07= D/C :Display d_c -> Connected to DC in Display Module
Device Tree configuration :
/*
* Shared hardware SPI bus on SPIM00 (EasyDMA, high-speed) — replaces the old
* bit-bang SPI. Two devices share the SCK/MOSI/MISO lines (P2.06/08/09) with
* separate chip selects:
* cs-gpios[0] = P2.10 -> SPI DEVICE — reg = <0>
* cs-gpios[1] = P2.03 -> GC9A01 display (via MIPI-DBI) — reg = <1>
* display refreshes arechunked (CONFIG_SPI_NRFX_RAM_BUFFER_SIZE) so the SPI thread reclaims the bus
* between chunks. The SPI Zephyr driver is bus-agnostic (Zephyr SPI API), so this
* is a pure devicetree change — no driver code change. */
&spi00 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&spi00_ecgdisp_default>;
pinctrl-1 = <&spi00_ecgdisp_sleep>;
pinctrl-names = "default", "sleep";
cs-gpios = <&gpio2 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>, /* P2.10 -> SPI device */
<&gpio2 3 GPIO_ACTIVE_LOW>; /* P2.03 -> GC9A01 */
};
* GC9A01 1.28" 240x240 circular display over the MIPI-DBI SPI transport (shares
* SPIM00 above). D/C = P2.07; CS via spi00 cs-gpios[1] (P2.03).
*
* RESET pin history: first tried P2.05 -- hard-wired on this DK's PCB to
* the onboard MX25R64 QSPI flash chip's cs-gpios (nrf54l15_cpuapp_common.
* dtsi); every reset pulse was also glitching the flash's chip-select. Then
* tried P2.00 -- Nordic's own connector-interface docs label this pin
* "SPI_IO3/External flash" (the flash's 4th QSPI data/HOLD# line), so
* likely also physically populated on the PCB. Using P1.14 for display reset,the way the flash depends on P2.00/P2.05. write-only
* restored on the mipi-dbi node -- see main.c for the disabled READID
* probe. */
/ {
mipi_dbi_gc9a01: mipi-dbi-gc9a01 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&spi00>;
dc-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; /* P2.07 = DISPLAY D/C */
reset-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* P1.14 = DISPLAY RESET */
write-only;
#address-cells = <1>;
#size-cells = <0>;
gc9a01: gc9a01@1 {
status = "okay";
compatible = "galaxycore,gc9x01x";
reg = <1>; /* CS index 1 -> P2.03 */
mipi-max-frequency = <DT_FREQ_M(32)>; /* clamped to SPIM00 max, original value */
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
width = <240>;
height = <240>;
display-inversion;
};
};
};
GPIO :
*************** BOOT LOG of SPI ***************
[DISP] GC9A01 ID probe: READID1(0xDA)=00 00 (ret=0) READID2(0xDB)=00 00 (ret=0) READID3(0xDC)=00 00 (ret=0)
[DISP] GC9A01: READY, SPI communication OK (bytes constant across all 3 reads -- bus transacted cleanly
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