Hi
nRF54L15-DK QFAAC0, ncs v3.4.0, project path: ncs\v3.4.0\zephyr\samples\boards\nordic\system_off
After compiling and flashing this example, the power-on reset (POR) power consumption is abnormal, measuring 169.37 µA. However, after pressing the RESET button on the DK board, the power consumption returns to normal, measuring 1.31 µA. The following patches were added via AI assistance, but the issue persists:
-
*(volatile uint32_t *)0x5005340C = 1; -
The following device tree patch:
text&vregmain { status = "okay"; regulator-initial-mode = <NRF5X_REG_MODE_DCDC>; };
# Normal power consumption
# abnormal power consumption
Hi, This is a known anomaly ([37] POWER: Current consumption might increase after pin reset or power cycle) that affects the nRF54L15. The symptom you describe �� high current after POR but normal current after pressing RESET �� matches exactly the documented errata condition. The workaround you've already applied (*(volatile uint32_t *)0x5005340C = 1;) is correct, but there is a second, equally important part of the workaround that is often missed: Ensure that 40 CPU cycles are executed before entering System OFF mode. [nRF54L15 Rev2 Errata #37] So the complete workaround is: *(volatile uint32_t *)0x5005340C = 1; /* Ensure at least 40 CPU cycles execute before entering System OFF */ You need to make sure there are at least 40 CPU cycles of execution between writing that register and the call to sys_poweroff(). If your code jumps to System OFF too quickly after the write, the anomaly can still manifest �� which is likely why you're still seeing the issue despite applying the register write. Checklist to verify: ? *(volatile uint32_t *)0x5005340C = 1; is called early in your application startup (before entering System OFF). ? At least 40 CPU cycles of code execute after that write and before sys_poweroff() is called. ? &vregmain DCDC mode is set in your devicetree (this helps with general power consumption but is separate from the errata fix). The POR case is the most sensitive because the device goes through its full power-on sequence before your code runs, and if System OFF is entered too quickly after that, the anomaly triggers. The RESET button case avoids the full POR sequence, which is why it behaves normally. If you can share how your main.c calls sys_poweroff() relative to the register write, that would help pinpoint whether the 40-cycle gap is being satisfied.