[Design Review] nRF52840 Custom Board - Schematic & Layout Check

Hi Nordic Support Team,

I have designed a custom board based on the nRF52840 and would appreciate it if you could review my schematic and PCB layout before I proceed with manufacturing.

Here are the specifications of my design:
- Target IC: nRF52840-QFAA (Package: QFN-48 / WQFN-48, 6x6 mm)
- Power Supply: 3.7V LiPo battery charged via TP4056 with DW01S/FS8205A protection, regulated down to 3.3V via external LDO (AP2112K-3.3) feeding into VDD pins. (Normal Voltage Mode)
- DC/DC Regulators: Enabled (DC/DC mode using external inductors L1 = 10uH on DCC and L2 = 15nH on DEC4/DEC6)
- HF Clock: 32 MHz external crystal (X1: 3225 12pF with 12pF load capacitors)
- LF Clock: 32.768 kHz external crystal (X2: 3215 12.5pF with 12pF load capacitors)
- Antenna type: 2.4 GHz Meandered Inverted-F PCB Trace Antenna (MIFA) with an LC matching network (L3 = 4.7nH, C13 = 1pF, C14 = 1.2pF, L4 = 2.2nH)
- Additional RF: Integrated PCB NFC antenna coil tuned with 91pF capacitors (C24, C26)
- PCB Stackup:
* Total Layers: 2-layer
* Total Board Thickness: 1.6 mm (Standard FR-4, Er ~ 4.4, 1 oz copper)
* Distance from Top Layer to Bottom GND Reference Plane: ~1.5 mm

I have attached the design archive containing:
1. Schematic (PDF & native design files)
2. PCB Layout (Gerber files / native design files)
3. Bill of Materials (BOM)

Specific points I would like feedback on:
1. RF transmission line layout and matching network values for the 2.4 GHz MIFA antenna.
2. DC/DC regulator circuitry routing (DCC, DEC4/DEC6 inductors and caps).
3. Decoupling capacitor placement and ground return path integrity under the MCU.
4. NFC antenna trace geometry and tuning capacitor values.

Thank you very much for your support!

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