Hi Team,
We are planning to use the following nRF52840 GPIOs for our current SPI interface, with the intention of migrating to QSPI in the future:
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CSn: P0.08
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CLK: P0.16
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IO0 / MOSI: P0.15
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IO1 / MISO: P1.08
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IO2 / WPn: P0.04
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IO3 / RESETn: P0.05
Could you please confirm if there are any restrictions when using these specific pins for standard SPI and subsequently QSPI?
Additionally, since the Nordic reference design recommends different default pins for QSPI, will using our custom pin assignment cause any side effects—such as limitations on maximum clock speed, potential RF/OTA degradation, or anything else?
Thanks and regards,
Kaushik Thumar
