nRF54L05 SAADC current at 2,048 Hz with two-channel scan

[Jonsiann]

I need the expected SAADC current for this configuration:

• Device: nRF54L05
• Supply: 3.0 V
• Internal DC/DC regulator enabled
• Resolution: 10 bit
• Two enabled analog input channels
• SAMPLE task triggered 2,048 times per second
• Each SAMPLE task converts both channels
• Total conversion rate: 4,096 conversions per second
• START triggered once before acquisition begins
• EasyDMA configured with a large sequential buffer
• STOP triggered only after the buffer is complete
• Internal SAADC timer disabled

Questions:

1. What is the incremental SAADC current while waiting between SAMPLE tasks?
2. After each two-channel scan finishes, are the converter clock, analog bias, reference, and high-frequency clock automatically gated until the next SAMPLE task?
3. Does keeping EasyDMA armed add continuous current between SAMPLE tasks?
4. What average SAADC current should I expect at 4,096 conversions per second?

The datasheet specifies 1.4 mA at 2 million conversions per second. I need the fixed current term and the conversion-rate-dependent term:

I_SAADC = C + M × conversion rate

Please provide C, or a measured current value at a low externally triggered sample rate.

[Pallavi Patil]

Hi Jonathan,

What is the incremental SAADC current while waiting between SAMPLE tasks?

In our documentation we only have measuremet for I_SAADC which is measured at maximun throughput 2 Msps

From your application, I can see that you are initialising EasyDMA at the start of acquistion ans stops only after the buffer has been written completeley. Thus, in your sytem EasyDMA stays enabled throughout the acquisition and will also remains active between samples in your configuration. Please correct me if my interpretation is not right. Your current profile will be dominated by the EasyDMA, typically ~1 mA. 

After each two-channel scan finishes, are the converter clock, analog bias, reference, and high-frequency clock automatically gated until the next SAMPLE task?

In your configuration, because the SAADC remains in the STARTED state with EasyDMA active throughout, we know that the high-frequency clock (HFCLK) stays requested and active between sample tasks. However, we dont explicitly detail low-level per-block gating for the internal converter clock, analog bias, or reference during inter-sample idle windows.

Since your data acquisition iis in the continuous mode  I can comment that the initial sample incurs tPWRUP​+tACQ​+tCONV​ while subsequent samples only take tCONV​. This pipelining behavior strongly indicates that the analog core does not fully power down between sample events when configured with an open buffer.

Does keeping EasyDMA armed add continuous current between SAMPLE tasks?

Yes, It will add to the additional current. If saving power is your main goal, it is better to start and stop the SAADC for each sample (START → SAMPLE → STOP). That lets the system completely turn off the clock and analog circuits between readings. 

What average SAADC current should I expect at 4,096 conversions per second?

We dont have enough information to calculate this. but I can take your problem with the team and check if they can make estimate. Further more, we also I dont have enoigh information on  C, or a measured current value at a low externally triggered sample rate. I can check and get back to you soon.

Regards

Pallavi

[Jonsiann]

Hi Pallavi,

Thanks for your response.

Your interpretation is correct. START occurs once, EasyDMA remains armed, SAMPLE is externally triggered 2,048 times per second, and STOP occurs after the complete buffer. Our objective is to complete the acquisition without waking the CPU for each two-channel scan.

Can you please ask the team for:

1. Estimated or measured current at 4,096 conversions per second in this configuration.
2. Whether EasyDMA preserves and advances its buffer position across repeated hardware-triggered START, SAMPLE, STOP cycles, allowing one sequential buffer to fill without CPU intervention.

Jon

[Pallavi Patil]

Hi Jon,

Thanks for confirming my interpretation.

To answer your question: 

Jonsiann said:

Estimated or measured current at 4,096 conversions per second in this configuration

In you application. when sampling continuously (keeping EasyDMA active and enabled between samples), EasyDMA dominates overall power consumption to the extent that the sampling frequencywill have minute contributuon towards  the average current draw, resulting in a baseline consumption around 1.24 mA. This value is stated for nRF52 series but I would expect value  ~/ > 1.24mA.

Jonsiann said:

Whether EasyDMA preserves and advances its buffer position across repeated hardware-triggered START, SAMPLE, STOP cycles, allowing one sequential buffer to fill without CPU intervention.

There is no auto-increment in the buffer pointer in the SAADC after it is stopped, so the CPU is required to update the buffer pointer before each triggering of the START task

Regards

Pallavi