I need the expected SAADC current for this configuration:
• Device: nRF54L05
• Supply: 3.0 V
• Internal DC/DC regulator enabled
• Resolution: 10 bit
• Two enabled analog input channels
• SAMPLE task triggered 2,048 times per second
• Each SAMPLE task converts both channels
• Total conversion rate: 4,096 conversions per second
• START triggered once before acquisition begins
• EasyDMA configured with a large sequential buffer
• STOP triggered only after the buffer is complete
• Internal SAADC timer disabled
Questions:
- What is the incremental SAADC current while waiting between SAMPLE tasks?
- After each two-channel scan finishes, are the converter clock, analog bias, reference, and high-frequency clock automatically gated until the next SAMPLE task?
- Does keeping EasyDMA armed add continuous current between SAMPLE tasks?
- What average SAADC current should I expect at 4,096 conversions per second?
The datasheet specifies 1.4 mA at 2 million conversions per second. I need the fixed current term and the conversion-rate-dependent term:
I_SAADC = C + M × conversion rate
Please provide C, or a measured current value at a low externally triggered sample rate.