Buffer overrun nrf24l01

Question

Hi,

I am using some nrf24l01s in a proof of concept (just because I have them, I know they are old). I am developing a TDM protocol for two-way radios, which requires 8000 bytes to be transmitted in 64ms. I am using 1 Mb/s and hope eventually to change to 2 Mb/s once I have got this debugged. I have all shockwave features disabled and am creating the on-air protocol myself. Basicaly I am using it as an RF modem. I created a test buffer and am sending 250 packets of 32 bytes with identical data. Problem is, the output as received on a monitor using an arduino and another nrf24l01 is getting the last byte of the previous packet added to the beginning of some packets. A logic analyser connected inline with the SPI port to the nrf24l021 board is showing that the SPI in the NXP FRDM-K64F is sending the correctly-framed data. My code is below. Any help greatly appreciated.

cheers

Nigel

void bulk_send(void)
{
	for (packet_count = 0; packet_count < 250; packet_count++)
	{
		transmit_buffer[((packet_count*32)+16)] = packet_count;
		clear_csn();
		command = 0xB0;					// write TX buffer No ACK
		send_spi(command);
		if (packet_count < 249)
		{
		    for (volatile uint8_t loop = 0; loop < 32; loop++)
		    {
		        pushr_val = SPI_PUSHR_CTAS(0) | SPI_PUSHR_PCS(1) | SPI_PUSHR_CONT_MASK;
		        pushr_val |= transmit_buffer[((packet_count * 32) + loop)];
		        {
		        	while (!(SPI1->SR & SPI_SR_TFFF_MASK)){};  // Wait until there is space available in the TX FIFO (TFFF flag)
		        	SPI1->PUSHR = pushr_val;
		        	SPI1->SR = SPI_SR_TFFF_MASK;
		        	while (!(SPI1->SR & SPI_SR_RFDF_MASK)){};
		        	volatile uint32_t dummy = SPI1->POPR;
		        	SPI1->SR = SPI_SR_RFDF_MASK;
		        }
		    }
		    set_csn();
		    GPIOB->PSOR = nrf24l01_CE_PINMASK; // Enable TX
		}
		else
		{
			clear_csn();
			command = 0xB0;					// write TX buffer No ACK
			send_spi(command);
			for (volatile uint8_t loop = 0; loop < 32; loop++)
			{
				while (!(SPI1->SR & SPI_SR_TFFF_MASK)){};  // Wait until there is space available in the TX FIFO (TFFF flag)
				pushr_val |= transmit_buffer[((packet_count*32)+loop)];	// Last byte: CONT = 0. This releases the Chip Select line automatically
				SPI1->PUSHR = pushr_val;
				SPI1->SR = SPI_SR_TFFF_MASK;
				while (!(SPI1->SR & SPI_SR_RFDF_MASK)){};
                volatile uint32_t dummy = SPI1->POPR;
				SPI1->SR = SPI_SR_RFDF_MASK;
			}
			set_csn();
			GPIOB->PSOR = nrf24l01_CE_PINMASK;// enable TX 2025-02-09 NWJ
		}
		if (debug) PRINTF("\r\n %d packets sent \r\n",packet_count+1);
		set_csn();						// packet actually gets sent here
		command = 0xE2;					// must clear out RX buffer in case it RX this TX packet
		clear_csn();					// 2025-04-22 NWJ put back in 2025-12-13 NWJ
		send_spi(command);
		command = (0xE1);				//flush TX buffer
		send_spi(command);
		set_csn();						// 2025-04-22 NWJ put back in 2025-12-13 NWJ
	}
	if (SPI1->SR & SPI_SR_RFDF_MASK)		// Drain the RX FIFO continuously to prevent an overflow state
	{
	     volatile uint32_t dummy = SPI1->POPR;
	     SPI1->SR = SPI_SR_RFDF_MASK; // Clear flag
	}
}