Looking the nRF7002 reference schematics in the datasheet and I'm wondering if you really have to use so many different capacitor values for decoupling. I would like to harmonize the values to reduce the number of lines in the BOM, which would reduce cost in manufacturing.
Are there any specifications about the minimum and maximum capacitance values?
The MLCC capacitance under DC bias is a related matter. As we all know, for example 100nF 0201 capacitor under 3V3 might be actually something like 60 nF. For bigger caps, the loss of capacitance is even worse. Therefore, it would be nice to know what are the real required capacitances under DC bias, rather than some nominal values.
Another thing I would like to protest, is that you show smaller capacitors connected in parallel with a larger one. It's based on wrong conclusion. All the caps are small SMD chips, and they all actually have ESL in the same range. A smaller cap isn't any better at high frequencies. In fact, having different capacitance values parallel connected may be dangerous: with the cap ESL and trace inductances they may build up harmful parallel resonances. My practice nowadays is to use a single value for parallel capacitors - it's much safer regarding unpredicted resonances.
