I'm not sure what happened to the formatting above
Hie
I agree, I am not able to read your case since some of the sentences are ending abruptly. Can you please create a new case with the same text. Can you paste the text in notepad/word and then copy the text to create the new ticket. It might help.
Regards
Pallavi
Interesting problem, and a very good description. There is an issue with sharing an AHB Slave between a peripheral DMA and the CPU stack, which may possibly be related as (as far as I know) the QSPI may not handle bus stalls well in relation to hardware clock handling, unlike the nRF54L15. Any stack access (interrupts or CPU) will take precedence over QSPI DMA access via the same AHB bus causing a bus stall which may not handle SCK well.
If two (or more) bus masters request access to the same slave device, the master with the highest
priority is granted the access first. Bus masters with lower priority are stalled until the higher priority master has completed its transaction.
There is a two stage AMLI (AHB Multi-Layer Interface) bus system in the nRF52840 and nRF52833 instead of one stage on the nRF52832 and this makes avoiding the stall on the nRF52840 more difficult to design around. The simple fix - assuming this is an issue in this case - is to separate QSPI AHB RAM from all other RAM which might be accessed during a transaction. Place the stack in any other RAM area, say RAM7; this would imply that placing both stack and QSPI DMA in (say) RAM7 would give an identical problem, but without knowing which other transactions can take place over shared RAM8 or shared RAM7 (whichever is chosen) that's hard to predict. I did some investigation on this issue when trying to precisely align multiple PWM outputs which was more difficult on the nRF52833 vs nRF52832. start-pwms-synchronous