How does balun circuit work?

[Eugene]

Tuning the nRF24xx matching network:

• The balun-function is done by the 180° degrees phase shift in L1. This causes the signals from the two ANT pins, 180° out of phase, to be added in the point between L1 and L3.

Could you clarify this moment? How it's done? Could you show waveforms to see what exactly happens here?

• The LO leakage in RX mode is mainly a common mode signal. The LO leakage is shorted by C4 via L2.

Why VDD_PA is used in this circuit and what's it intended for? What's happening in this part of the circuit?

[Øyvind Karlsen]

Hi,

Good question, I will attempt to answer this as in detail as I can.

First off lets start with the motivation for using differential outputs. Differential signals have a inherent noise immunity that is higher than for a single ended solution. One of the major factors here is the reduced coupling noise. Since the same noise is coupled (added) to both wires of the differential signal we see little to no change in the difference between the two wires, which means that we have increased noise immunity.

When you want to use the chip with a single ended antenna, you will have to use a balun (balanced to unbalanced) to transform the differential signal. Next lets consider the differential signal.

A differential signal is made by splitting a signal in two and then inverting one of the resulting halves. Inversion in the frequency domain is the same as a phase shift of 180 degrees. We call the two halves modes, hence if noise can be considered common mode, it exists in both halves with the same voltage offset.

So lets move on to understanding how L1 introduces this 180 degree phase shift. If you simulate the frequency and phase response for a 2.45 GHz signal with this 8.2 nH inductor you will see that it only introduces a 90 degree phase shift. This is because there are a lot of parasitic effects from the SoC, pad capacitance, bond wire inductance and capacitance, etc. The end result is that the L1 value gives a power output that is correct.

VDD_PA is the supply voltage for the amplifier transistors. For DC voltages the capacitors C3 and C4 appear as open circuits and the inductors L2 and L1 appear as shorts. This means that DC supply voltage is delivered to ANT1 and ANT2 from VDD_PA.

Undesired leakages, such as the LO leakage described are shorted to ground in C3 and C4. C3 and C4 are capacitors with good RF properties, which allow them to conduct a wide range of RF frequencies. With recent improvements in process technology we have been able to get the same performance out of integrated components, this has allowed us to move the differential to single ended, as well as the supply network inside the chip (nRF52), lowering the toal BoM for the end user.

For the target frequency of ~ 2.44 GHz the impedance of the supply network is infinite, this means that as little as possible of the desired RF energy is lost inside the supply network. However for all other frequencies, the supply network appears as a short to ground. This short effect can be tuned so that it is stronger at a certain frequency, for example the LO leakage that needs to be limited.

Hopefully this answers your question. Best regards,

Øyvind

[Eugene]

So L1 gives us only 90 degrees phase shift as expected and other 90 degrees we get with help of parasitic components. That's why we should strictly follow PCB design guidelines given by Nordic. Right?

Could you explain why we need to supply RF PA with external network (because of the chosen tech. i suppose)? VDD_PA separated with ANT pins via LC filter because of the RF noise that can penetrate into the chip if we connect VDD_PA directly? I'm i right?