nRF51822 spi master transfer uncertain delay between bytes

[Jason]

Hi,

I am using nRF51822 spi as a master to communicate with the AFE. Four bytes need to transfer each read or write process. I use nRF51_SDK_10.0.0_dc26b5e.

Configuration:

NOTE: Blocking mode is used void spi_master_init(void) { uint32_t err_code = NRF_SUCCESS;

nrf_drv_spi_config_t config =
{
    .ss_pin       = NRF_DRV_SPI_PIN_NOT_USED,
    .irq_priority = APP_IRQ_PRIORITY_LOW,
    .orc          = 0x00,
    .frequency    = NRF_DRV_SPI_FREQ_1M,
    .mode         = NRF_DRV_SPI_MODE_0,
    .bit_order    = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST,
};

config.sck_pin  = SPI0_CONFIG_SCK_PIN;
config.mosi_pin = SPI0_CONFIG_MOSI_PIN;
config.miso_pin = SPI0_CONFIG_MISO_PIN;
err_code = nrf_drv_spi_init(&m_spi_master_0, &config, NULL);	// If NULL, transfers will be performed in blocking mode

APP_ERROR_CHECK(err_code);

}

Send process:

uint32_t set_afe_reg_value(uint8_t num_register, uint32_t register_value) { uint8_t spi_tx_buf[4]; uint8_t dummy_rx_buf[4];

uint32_t err_code;

/* Set SPI transmit buffer */
spi_tx_buf[0] = num_register;						// Address
spi_tx_buf[1] = (uint8_t) ((register_value >> 16) & 0xFF);	// Data[23..16]
spi_tx_buf[2] = (uint8_t) ((register_value >> 8) & 0xFF);	// Data[15..9]
spi_tx_buf[3] = (uint8_t) ((register_value) & 0xFF);		// Data[7..0]

/* Set chip select signal active before SPI transfer */	
nrf_drv_gpiote_out_clear(SPI0_AFE_CS_PIN);
	
/* Start SPI transfer */	
err_code = nrf_drv_spi_transfer(&m_spi_master_0, spi_tx_buf, 4, dummy_rx_buf, 4);
	
/* De-select chipset */
nrf_drv_gpiote_out_set(SPI0_AFE_CS_PIN);
	
return err_code;

}

The tested code:

set_afe_reg_value(AFE_REG0, 0x00000001);
set_afe_reg_value(AFE_REG1, 0x00001010);

there is a delay(not short) between the third bytes transmit and fourth byte during the second set register value process as shown below:(/attachment/9319e775c3ae331f05fd75f7b4169ad8)

[Kenneth]

Hi, "Blocking" means that the nrf_drv_spi_transfer() will not return until the transfer is done. However the execution might still be interrupted by higher level application interrupts and/or softdevice events. Could this explain your observation?

[Jason]

• Yes, I want to use blocking mode. I don't want to return during spi transfer.
• I don't program the softdevice stack, and also don't initialize ble_app_initial. Additionally, I write a simple spi transfer, write one byte, read one byte and wait for NRF_SPI_EVENT_READY event, I found even in byte-by-byte transfer, the NRF_SPI_EVENT_READY event would delayed uncertain. I agree with what you mentioned, there may higher level interrupts, but I don't know what would be ?

[Kenneth]

Have you used the spi example from the latest nRF5 SDK v11? See \examples\peripheral\spi

To make it blocking set event handler to NULL when calling nrf_drv_spi_init(). Do you see the same delay with this example?