watchdog reset interaction with NVMC page erase

[pabigot]

Per the nRF51822 product specification the NVMC ERASEPAGE operation takes up to 22.3 ms, about 730 ticks of a 32 KiHz clock. This is 365x the maximum delay between the watchdog TIMEOUT event and a system reset.

I expect that if an nRF51 loses power while the NVMC is executing ERASEPAGE it is possible that the erase will not be complete. True?

The question: If a watchdog TIMEOUT event triggers a reset while NVMC is executing ERASEPAGE is there any possibility that the page will not be fully erased when the reset competes?

(I did find this question but the answer doesn't address this potential failure mode.)

[Stian Røed Hafskjold]

The answer in the link you posted is correct in the sense that the WDT keeps counting during a flash erase/write, but if the TIMEOUT event is generated during flash operation, the watchdog reset itself will be delayed until it is finished. So it will never erase only part of the page.

Also, if you have a WDT interrupt handler that looks something like this,

void WDT_IRQHandler(){
    NRF_NVMC->ERASEPAGE = 0x3fc00;
    *((uint32_t*)0x0003FC00) = 0;
}

the ERASEPAGE will be completed, but then the chip will reset before the next line, so it never writes 0 to that address.