nRF52 cache

[jsleeman]

Hello everyone,

I am using the nRF52832 rev 1, i am not using the softcore. When the cache is enabled as below, the performance actually seems to get worse.

F_NVMC->ICACHECNF = ((NVMC_ICACHECNF_CACHEEN_Enabled << NVMC_ICACHECNF_CACHEEN_Pos) |
                           (NVMC_ICACHECNF_CACHEPROFEN_Enabled << NVMC_ICACHECNF_CACHEPROFEN_Pos));

I then tried with profiling enabled, this didn't help the situation.

I did get the following information for: IHIT: 0x47e0b97d IMISS: 0x01d6bb47

Considering the misses is a lot lower than the hits, i would expect performance to improve.

I also searched through the examples in the nRF5_SDK_11.0.0_89a8197 library, the ICACHECNF register was never set.

Am i setting the register correctly? Has performance benefits of the cache been tested?

Thanks, James

[Anders Strand]

When using a softdevice, it will turn on the Cache by default. The application is free to turn it off if it wants.

Cache will in most applications bring a performance increase. Spending less time waiting for flash operations will in most cases also decrease the current consumption of an application.

Information about the flash and cache can be found here. Here you can see timings of flash reads and writes.

[jsleeman]

The webpage you have provided a link to, provides timings for write, erase page and erase all, however nothing is mentioned about write times. Is it missing from the webpage? Or could you point out something i could search for in the page to help me find it. Many thanks, James.

[Anders Strand]

Hi. The flash reads will be as fast as RAM reads. I could not find any numbers at this time, but you can assume it to be very fast. Will you need the excact numbers?

[jsleeman]

Hi. It's not essential but it would be useful as our timings are very tight, and it would be good to work out how much time everything is taking. Thanks.

[tesc]

Hi.

Just wanted to add that in the nRF52832 Product Specification the section CPU performance lists the following numbers for CPU wait states when running from flash and RAM:

flash w/o cache: min. 0 max. 2
flash w/ cache: min. 0 max. 3
RAM: max. 0

The best and worst case numbers for flash access are due to difference in frequency between CPU and flash. This means flash reading times are in the range 0 to 2 cpu cycles without cache, and in the range 0 to 3 cpu cycles including a cache miss.

Regards, Terje