nRF24LE1 control PAW3205DB by two-wire spi

[Cao Jean]

I'm just using nRF24LE1 to make 2.4G wireless mouse, mouse sensor is PAW3205DB-TJ3T. But i got a problem, PAW3205DB-TJ3T uses two-wire spi(SCKL+SDIO), nRF24LE1 only supports four-wire spi. So, what can i do?

---------update-------

I'm very grateful to you for your reply.I really want to give up.Because i have asked many people but nobody answer me.

This is the PAW3205DB Datasheet contains protocol and timing. link: pan.baidu.com/.../1kVIYrLP PWD: s7mp

I have try to use bit-bang the interface. But it has some problem. My code,read the ID to test communication is ok. RF_Mouse_PAW3205.zip

sometime,it will be ok when the mouse don`t move. I can read 0x30 at address 0x00, read 0xd1 at 0x01.

It will be fail when the mouse move. I try many times...

Detail logic: normal.logicdata abnormal.logicdata

[RK]

Can't see another solution except to bit-bang the interface. Is there even a proper datasheet for the PAW3205DB? I can find one which has the registers listed, but says nothing at all about how to use them nor the wire protocol, timing or anything else.

[Cao Jean]

Thank you RK, I have update the detail. Can you help me again?

[RK]

not really sure what to suggest. The logic outputs seem reasonable but it's very possible the chip is getting out of sync with it and you're getting some real random stuff. You might want to try doing the re-sync sequence mentioned in section 6.2 of that manual at some point during the stream and see if it helps. I was trying to work out whether the chip sees any of those things as a reset, but it seems it requires at least 1us low followed by a long high on the clock line and I think all your lows are shorter than that.

Regrettably the Salae decoder doesn't really decode that protocol so you can't easily see if you're dropping out of sync, but it seems you have to be. Something odd happens around 1.493437 seconds into that trace, the data line blips without a clock cycle, after that things seem to go wrong.

[Cao Jean]

It really drops out of sync, i can see the value is wrong by send it to nRF24LU1. P0.5 and P0.7 can't use to bit-bang SPI?

[RK]

I'm sure they can - it's a simple clocked protocol. Since this chip combo is used everywhere, including the reference design, and since the chip has no support I can find for half-duplex SPI, someone else must have gotten it to work.

[RK]

One comment here - I was looking into something completely different to do with running Secure Digital (SD) cards using an SPI interface and came across an idea to tie MISO and MOSI together with either one or two 10k resistors and connect the combination to the single SDIO pin. I think the right way may be to connect the SDIO directly to MOSI and via a 10K resistor to MISO. When you are sending data you receive the data you send as both MOSI and the SDIO pin should be high impedence, when you receive, you clock out 0s on MOSI to hold it low and the SDIO pin actually drives it to the proper level.

I have no idea if this works, but I've seen a couple of circuits suggesting it might. It's not good enough for me to try with the SD implementation I have to work with but I remembered this thread

MISO ------------- SDIO--|
MOSI ----wwww ---- SDIO--|
           10k