About PPI priorities

[Paul]

We all know that PPI can have the same event to trigger other tasks. But I couldn't find any official document explaining the priorities/timing of those tasks linked to the same events.

My understanding and test are showing the lower PPI channel numbers have the high priorities which will happen first.

I just wanted an official answer to confirm this finding is true.

Thanks

[tellg]

Hello

I have a similar usage on the nRF52: TIMER CAPTURE and TIMER CLEAR as shown below

NRF_PPI->CH[0].EEP = (uint32_t)&NRF_GPIOTE->EVENTS_IN[0];
NRF_PPI->CH[0].TEP = (uint32_t)&NRF_TIMER1->TASKS_CAPTURE[0];
NRF_PPI->FORK[0].TEP = (uint32_t)&NRF_TIMER1->TASKS_CLEAR;

// Enable PPI channel 0
NRF_PPI->CHEN = (PPI_CHEN_CH0_Enabled << PPI_CHEN_CH0_Pos);

The nRF52 ref manual does not say anything on priorities between CAPTURE and CLEAR tasks Will I risk losing the capture on the nRF52 (silicon rev 1) ?

At least on my development kit, PCA10040 V1.1.0, the capture works fine

[Stefan Birnir Sverrisson]

Hi

The designer says that it should work the same every time at least. There should be no race condition. So if you have it working already, it should do that reliably all the time.