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I2S 32-bit word size

Hello,

I am struggling with interfacing an I2S digital microphone to the nRF52. To be more concrete, it is the Knowles SPH0645LM4H-B. I connected it as suggested in this thread. In the data sheet of the microphone it says:

The SPH0645LM4H microphone operates as an I2S slave. The master must provide the BCLK and WS signals. The Over Sampling Rate is fixed at 64 therefore the WS signal must be BCLK/64 and synchronized to the BCLK. Clock frequencies from 2.048Mhz to 4.096MHz are supported so sampling rates from 32KHz to 64KHz can be had by changing the clock frequency. The Data Format is I2S, 24 bit, 2’s compliment, MSB first. The Data Precision is 18 bits, unused bits are zeros.

I find this contradictory with the figure also provided in the data sheet of the microphone:

image description

In the image it is clear to see that WS toggles first after 32 clocks, which -for me- means, the word size is 32 bits (18 bits data, 6 bits set to 0, and 8 further bits floating).

The problem is that the nRF52's I2S interface does not support 32-bit word size.

/**
 * @brief I2S sample widths.
 */
typedef enum
{
    NRF_I2S_SWIDTH_8BIT  = I2S_CONFIG_SWIDTH_SWIDTH_8Bit,  ///< 8 bit.
    NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
    NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit,  ///< 24 bit.
} nrf_i2s_swidth_t;

No matter what settings I try with the available 8, 16, or 24 bit word-size, I can't get all the relevant data bits from the microphone's data stream.

Any ideas how to solve this problem? Or are these two components (nRF52 and Knowles mic) simply incompatible?

Thank you in advance! NewtoM

Parents
  • Hello All,

    I think there is a work-around of sorts now that addresses the issues experienced here... Specifically, the term "24-bit" is misleading. 24-bit I2S microphones output 24 data bits per stereo channel but require 32 SCK pulses per channel to function properly. So, the stereo I2S frame needs to be 64 SCK pulses wide. Like everyone else, I was attempting to collect audio data from a modern 24-bit I2S MEMS microphone and ran into the hard-coded limitation of 48 SCK pulses per stereo I2S frame in I2S master mode. The I2S frame will never be 64 SCK pulses wide In master mode but in I2S slave mode the nRF52 will properly decode the 24 data bits per channel even if the the frame is 64 SCK pulses wide. After reading the I2S protocol spec, It dawned on me that there really is precious little difference between I2S master and slave modes... Just where the LRCK and SCK pulses come from.

    My solution was to augment the PWM library to set the PWM carrier period directly in 16MHz ticks, not milliseconds. So I use two PWM channels; one to generate SCK and the other to generate LRCK and connect the PWM outputs to the I2S SCK and LRCK pins. I set the LRCK PWM channel period to be 64X that of the SCK PWM chanel period. I have a functioning peripheral application for SDK 13.0.0 and the pca10040 DK board located here:

    github.com/.../nRF52_24-bit-_I2S_Microphone_Audio_Recording_Utility

    I was using the Invensense ICS43432 microphone. There is a sample ".wav" audio file that demonstrates typical audio quality....

    This may be considered as an ugly work-around but it does work and doesn't require any other external devices to generate the clock signals...

    Best Regards, Greg Tomasch

  • Does anyone know if this I2S Master clock issue has been addressed (fixed) in the nRF-52840 device?

  • I2S behavior is similar on nRF52832 and nRF52840.

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