We are in process of identifying the right hardware for our project and considering nrf52832 as the core processor. For our requirements, we need to use external serial NOR flash to record few measurements continuously in external flash and play pre-saved audio files from the external flash using nrf52 I2S (with EasyDMA) interface.
We have situations where we often need send some measurements over ble, while playing the audio file from this external NOR flash via I2S and writing few measurements in the external Flash, all of these simultaneously.
After doing a bit of reading about nrf52, we have the following concerns for choosing it as our processor.
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NRF52 SPI-M (with EasyDMA) has limited Tx and Rx buffer size (only 256 bytes) and the page size of serial NOR flash is usually about 256 bytes. We may not be able to read/write one full page of the external flash by one SPI command as some initial bytes in the Tx buffer are meant for spi commands. This limitation makes increases the SW complexity and is not very efficient. Just wanted to know if any one had similar situations and what is the optimal method to handle the SPI communication.
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The serial NOR Flash chips needs SS/CS (slave select/chip select) pin return to high state at the end of the last byte transaction on the SPI bus for most its critical commands other wise these commands will be rejected but the external Flash. From the nrf documentation, we see that the SS/CS pin has to be controlled by the CPU not by the peripheral. We foresee that when ble is active, the CPU is fully occupied during the radio interrupts and the precise timing of CS/SS pin states can't be achieved. Is is possible to achieve the precise control on the timings of SS/CS pin states, all the time even when the ble is active.
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To play the audio files from flash, we planned to use double buffers. While reading one of this buffer from flash, the other could be used to play the audio via I2S. Maximum allowed buffer size would be limited to 251 bytes (as the SPI read command takes about 5 bytes). Once the received buffer is full, we need to pull the CS pin low to indicate the external flash to stop transmission. Would the SPI clock stops when the receive buffer is full ? If not, if we fail to pull the SS/CS pin high and if external flash keeps transmitting the data, will the received buffers are over-written ?
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Having a buffer size less than 251 bytes is too little time (less than 8ms for audio sample rate of 16KHz with 16 bit samples or 12ms with 12bit samples, we can't go below this rate ). Would this time be enough to assign the next buffer in I2S driver (with EasyDMA) while ble is active with out a drop out of the audio. We can't also increase this buffer size, as it will increase the delay in playing the audio.
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Could there be any other concerns apart from the above. Are there any other methods to solve the above issues. Is it better to look for a different processor ?
At this point, with the above concerns, not sure if we should go ahead with nrf52 as we can't afford to change the hardware at a later point of time. We might be missing some information about the nrf52 capabilities. Any comments/suggestions would be of great help.
Thank you
