What are the expected wait states when reading data from RAM and FLASH on the nRF52? This is stuff on the DCODE bus.
What I'm seeing whilst profiling is a load instruction eg
ldr r1, [ r2, r3 ]
from RAM is taking 3 cycles (so 2 wait states) and one from FLASH is taking 5 cycles (so 4 wait states).
This appears to be confirmed if I enable the DWT_LSUEVTENA and check the DWT_LSUCNT register after each read, it increments by 2 for each RAM read and 4 for each FLASH one.
I can't find anything in the manual about read wait states for RAM or FLASH, only wait states for CPU instruction processing, however for FLASH that maxes out at 2, but then again CPU fetches are on the ICODE bus and are pipelined so it may not be a correct comparison.
Are 2 wait states for RAM read and 4 for FLASH read correct?
