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NVIC does not tail-chain to PendSV ISR

I'm trying to implement context switching from handler mode to thread mode using PendSV. I set the PendSV pending bit inside an ISR with SCB->ICSR = SCB->ICSR | SCB_ICSR_PENDSVSET_Msk. After setting the PendSV pending bit, I can see that the PendSV exception is pending: SCB->ICSR = 0x10000813 (I think the ISRPREEMPT bit should be set as well but it's not).

NVIC should tail-chain to my PendSV handler before unstacking. Instead ISR unstacking occurs, a return to exception is executed, and a few thread-level instructions are executed, before the PendSV handler is called.

The SoftDevice is present but has not been enabled.

Any ideas on what might be causing this? Thanks.

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  • I am confused here, i tested this and also found that tail chaining is not happening not only with PendSV but with any interrupt... but this is a ARM Cortex feature right. You are writing directly to SCB block and not using any of the NRF features. I will have to look more into this tomorrow but I am not sure how much i should trust the debugger on this. Is there any other way you verify this without using debugger/breakpoints

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  • I am confused here, i tested this and also found that tail chaining is not happening not only with PendSV but with any interrupt... but this is a ARM Cortex feature right. You are writing directly to SCB block and not using any of the NRF features. I will have to look more into this tomorrow but I am not sure how much i should trust the debugger on this. Is there any other way you verify this without using debugger/breakpoints

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