I compiled the ble_app_cts_c project of the SDK12 using the Segger Embedded Studio having as target the PCA10040 board (S132 stack). After spending some time to convert the Keil project to a Segger project, I was able to compile it without any error or warning. But somethings is not right, because whenever I try to run the program, it crashes in the page_identify function of the fds.c file (which is called from peer_manager_init). The debbuger looses the tracking in the first line of this function ...
My suspicious is that the project is not correctly configured on the Segger IDE, more precisely with the memory settings.
I already tested other projects with the Keil IDE and this problem doesn't happen. Unfortunately the projects that use whitelist exceed the limit of the 32K of the Keil IDE.
The section placement macros are defined this way:
And the memory_map is defined this way:
I also added some entries in the flash_placement file to surpass a linkage error:
Have you any ideia about where is the problem?
Thanks for your attention,
See this answer. You need to change thumb_crt0.s (right click and choose import first to save a copy in the project folder) to copy the fs_data from FLASH into RAM. Like RK suggested:
ldr r2, =__tdata_end__
# ADD HERE ...
ldr r0, =__fs_data_load_start__
ldr r1, =__fs_data_start__
ldr r2, =__fs_data_end__
# TO HERE ...
I got the same error as you when I did not do this.
In the SDK this is done in a slightly different way. Instead of using data_end as the end of the data section, bss_start is used, such that the user can add their own initialized data section. From the gcc_startup_nrf52.s file:
/* Loop to copy data from read only memory to RAM.
* The ranges of copy from/to are specified by following symbols:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
* the user can add their own initialized data section before BSS section with the INTERT AFTER command.
* All addresses must be aligned to 4 bytes boundary.
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__