• State Verified Answer
  • Replies 10 replies
  • Subscribers 62 subscribers
  • Views 6458 views
  • Users 0 members are here
Attachments (0)
Nordic Case Info
  • Case ID: 101655
Options
This post is older than 2 years and might not be relevant anymore
More Info: Consider searching for newer posts

LDO current consumption, low voltage mode.

cocoa

Hi Nordic guys,

How much is the current consumption of the LDO only (quiescent current), without DC / DC converter, in uA? How much is dropout voltage and PSRR (ripple rejection) ?

When powering nRF51822 in low power mode, LDO has a quiescent current or is true disconnected?

What are the advantages and disadvantages when powering nRF51822 in low voltage mode ?

How much is leakage current of a gpio pin when enabled as output and as input ?

Thanks.

-c

Parents
  • 0

    I don't have a number for the current consumption of the LDO itself, since you will never see just this. The lowest current consumption you'll see for the chip in total is system off current with no RAM retention, which is specified to be 0.6 µA.

    I'm not quite sure what you mean by low-power mode, but if you mean low-voltage mode (as described in section 3.4.1 in the PS), this will incur an additional 1 µA current consumption in system on and system off. In addition, the ripple tolerance is lower.

    In practice, I'd therefore recommend using the regular mode, the internal LDO, on current chip revisions. This gives the lowest current consumptions in sleep, and the best ripple tolerance. As you probably know, the DC/DC is currently not recommended for use unless your chip continuously draws enough current to justify having it on. See section 11.1.1 of the RM for details.

    The leakage current of any GPIOs is negligible, in the femtoampere range or lower.

Reply
  • 0

    I don't have a number for the current consumption of the LDO itself, since you will never see just this. The lowest current consumption you'll see for the chip in total is system off current with no RAM retention, which is specified to be 0.6 µA.

    I'm not quite sure what you mean by low-power mode, but if you mean low-voltage mode (as described in section 3.4.1 in the PS), this will incur an additional 1 µA current consumption in system on and system off. In addition, the ripple tolerance is lower.

    In practice, I'd therefore recommend using the regular mode, the internal LDO, on current chip revisions. This gives the lowest current consumptions in sleep, and the best ripple tolerance. As you probably know, the DC/DC is currently not recommended for use unless your chip continuously draws enough current to justify having it on. See section 11.1.1 of the RM for details.

    The leakage current of any GPIOs is negligible, in the femtoampere range or lower.

Children
No Data
Related