LDO current consumption, low voltage mode.

[cocoa]

Hi Nordic guys,

How much is the current consumption of the LDO only (quiescent current), without DC / DC converter, in uA? How much is dropout voltage and PSRR (ripple rejection) ?

When powering nRF51822 in low power mode, LDO has a quiescent current or is true disconnected?

What are the advantages and disadvantages when powering nRF51822 in low voltage mode ?

How much is leakage current of a gpio pin when enabled as output and as input ?

Thanks.

-c

[cocoa]

Thank you Ole, I've questions again.

In the event that the supply voltage was 1.8V, LDO is disconnected or continues to consume the current Iq (quiescent).

I do not want to evaluate the power consumption in the case of System Off chip but functional.

When LDO is working, (i.e. 3.3 V as Vin) how is its consumption to reduce the voltage down to 1.8V, assuming the fact nRF51822 internal operating voltage is 1.8V and this is why there is an LDO inside.

I can not understand how it can consume less using internal LDO respect to an external power supply of 1.8V, which should exclude LDO.

Can I exclude forcibly the internal LDO using a register as in the case of the DC / DC converter?

Can you help me understand better?

Thank you.

-cocoa