How do correlate sinking and sourcing high drive current on nRF51422?

[tobias zvonc]

If, for example we would source 10 mA on 2 pins (2 x 5 mA), how much current can we sink on high drive pins?

Is that 15 mA overall sinking and sourcing (which seems like it doesn't make sense) or we can sink 15 mA and source 15 mA?

[tobias zvonc]

Thank you, but we don't need a safe answer, we need a precise answer (and explanation would be OK :) ).

For example, if we are sourcing 5mA on 2 pins, our high side internal FET-s and VDD trace inside a chip is "under stress". Why would that affect our sinking current capability (during sinking, lower side FET-s and VSS traces are under stress)?

Another question - does high/standard/disconnect drive definition for pins have affect on TWI drive? I.e. if we have TWI interface ono 3.3V with 2k2 pullups, are we obligated to define "high 0, disconnect 1" drive? Or TWI has its own drive configuration? If does, what is maximum sinking current (if it is not 0.5mA)?

EDIT: We would sink current on some other pins, not on those who are sourcing.