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nRF52832- why when using nrf_drv_spi with an ADXL362 I need to set the clock in high drive (H0H1)

Hello!

I am working on a project. The goal is to retrieve every seconds some acceleration data from the ADXL362 accelerometer.

I configured the spi in blocking mode by passing NULL as event handler nrf_drv_spi_init(_spi, &_spi_config, NULL);

This method will use the information inside the _spi_config structure to set the pins with this configuration:

PIN_CNF[MOSI] = 0x00000003
direction:output, input: disconnect, pull: disabled, drive: S0S1, sense: disabled

PIN_CNF[MISO] = 0x00000000
direction:input, input: connect, pull: disabled, drive: S0S1, sense: disabled

PIN_CNF[CLK] = 0x00000001
direction:output, input: connect, pull: disabled, drive: S0S1, sense: disabled

PIN_CNF[SS] = 0x00000003
direction:output, input: disconnect, pull: disabled, drive: S0S1, sense: disabled

But when I try a dummy transaction like read (0x0B) the register with the acceleromter ID (0x00), I should have 0xAD.

Instead I have this: image description

S0S1.JPG

I thought that The MISO pin was not really disconnected but after several tries I found that if I modify the clock pin config to work in high drive:

PIN_CNF[CLK] = 0x00000301
direction:output, input: connect, pull: disabled, drive: H0H1, sense: disabled

I have now a good communication transaction with the accelerometer: image description

H0H1.JPG

Any idea why the clock config influence the MISO signal?

My project need to be low power, therefore I should not use the clock pin in high drive mode.

Another guy have the same problem: devzone.nordicsemi.com/.../

Thanks for your help,

Cyril Praz

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  • Here is the answer from a nordic application engineer:

    Hi,

    Comparing the rise and fall time of a GPIO on the nRF51 vs. the nRF52, that data is not easily available. Although nRF52 uses a similar architecture the actual pad drivers are very different (since nRF51 use 180nm vs nRF52 use 55nm).

    Simulation on a large capacitor load (100nF @ 3V) show that the rise and fall time on the nRF52 is almost 3x that of nRF51 (60ns->150ns). So it might be that the nRF51 just were able to meet the requirement in standard drive, but on the nRF52 you need to use high drive. Overall though I don't expect using high drive will increase current consumption, as it only affect the rise and fall times (you are not loading the line with resistive load).

    Best regards,

    Kenneth

Reply
  • Here is the answer from a nordic application engineer:

    Hi,

    Comparing the rise and fall time of a GPIO on the nRF51 vs. the nRF52, that data is not easily available. Although nRF52 uses a similar architecture the actual pad drivers are very different (since nRF51 use 180nm vs nRF52 use 55nm).

    Simulation on a large capacitor load (100nF @ 3V) show that the rise and fall time on the nRF52 is almost 3x that of nRF51 (60ns->150ns). So it might be that the nRF51 just were able to meet the requirement in standard drive, but on the nRF52 you need to use high drive. Overall though I don't expect using high drive will increase current consumption, as it only affect the rise and fall times (you are not loading the line with resistive load).

    Best regards,

    Kenneth

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