reuse_TX_PL command timing diagram

[David]

Hi all,

I'm trying to use NRF24L01, using REUSE_TX_PL command, the data sheet says as long as CE keep high, the chip will transmit the payload continuously, what i wondering is whether there is a delay between packet frame or not? or is there any body can help to provide me timing diagram for that command similar to "Enhanced shockBurst Timing" figure 13, page 38 in the NRF24L01 datasheet

davids

[David]

Hi Hakon,

the reason I'm doing that way is to avoiding PLL lock time (130us) every time I repeat transmitting the same data payload (1 frame = preamble + 3byte address + 2byte data = 6byte only) that mean I don't want the chip go to standby-1 every time it finish transmitting one payload packet, but it will directly repeat the transmission with no delay at all. is it possible? do I'm doing the right way?

best regard

davids

[Håkon Alseth]

Hi David,

That should not be an issue if CE is kept high under the operation. Are you seeing that this does not work? You can scope line "VDD_PA", which is the feed-line to the internal power amplifier, to see if the transmission is back-to-back (is high over 150 us, depending on data-rate used)

Best regards Håkon