Clarification of t_CSD and t_CC of SPI slave

[Remo]

Hi all

The nRF51822 product specification V3.2, chapter 8.8, specifies the times t_CSD and t_CC of the SPI slave peripheral for the low power mode and for the constant latency mode.

The reference manual states that these modes are sub power modes when the CPU is sleeping. Therefore, I would like to know which time applies when the CPU is running during SPI communication?

Kind regards

[Ole Bauck]

Hi Remo,

See chapter 3.4.2.2 in the Product Specification. There it is specified which resources that are kept on when using constant latency mode, which includes 1V7 regulator, 1V2 regulator and HFCLK (RC or XO). In section 8.3 "Block resource requirements" you can see that the CPU require these resources, which means that they will be on when the CPU is running.

Therefore the constant latency mode time applies when the CPU is running.

Ole

[Remo]

Hi Ole, thank you very much for the clarification!