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"Ideal" supply voltage for nRF52 to maximize efficiency?

I have the opportunity to select the voltage of the power supply feeding an nRF52. There no other chips in the system, thus there are no other constraints on the voltage. I realize that the nRF52 manages the usage of its internal LDO and DCDC converter; that's not the issue. Within the acceptable range of supply voltages for the chip, is there one which maximizes efficiency, taking into account the efficiency of the DCDC converter, etc.? If we were running only on the LDO, then a lower input would make sense, but the DCDC complicates the picture. I've not been able to find as much data on this topic as exists for the nRF51.

Thanks, Scott

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  • Hi,

    For the nRF52 we have an online power profiler. Play around with the parameters there to see what will have the most impact. Generally the closer you get to the final voltage of a converter the less loss you will have and the more efficient your supply system will be.

    Best regards,

    Øyvind

  • Hi Øyvind, Thank you for pointing me at the profiler. I've played with it, and the average current appears to be linear with supply voltage, with the lowest current at the highest voltage. I note that the DCDC converter is assumed to be enabled. I have a couple of questions as a result:

    1. Does the model assume the DCDC is always operating during the period of the calculation, or is it being turned on and off under the control of the PMU?
    2. In our application, there will be long periods of idleness. Is it correct to assume that the PMU will decide to turn off the DCDC during those periods and instead enable the LDO?
    3. Am I correct in thinking that, when running on the LDO, the lower supply voltage would be preferable to minimize the voltage drop across the LDO?

    Thanks, Scott

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  • Hi Øyvind, Thank you for pointing me at the profiler. I've played with it, and the average current appears to be linear with supply voltage, with the lowest current at the highest voltage. I note that the DCDC converter is assumed to be enabled. I have a couple of questions as a result:

    1. Does the model assume the DCDC is always operating during the period of the calculation, or is it being turned on and off under the control of the PMU?
    2. In our application, there will be long periods of idleness. Is it correct to assume that the PMU will decide to turn off the DCDC during those periods and instead enable the LDO?
    3. Am I correct in thinking that, when running on the LDO, the lower supply voltage would be preferable to minimize the voltage drop across the LDO?

    Thanks, Scott

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