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What are SWI0~5_IRQn and time slot?

My apologies, but I just want someone to give me a quick brief on what are these things and how they work. AFAIK, the nrf51xxx series SoCs render limited, sporatic radio availability to user applications, using a scheduling mechanism, and the radio time allocated is often called a "slot". The thing is, what are SWIx ?

Also, where are the documents detailing the NVIC on nrf51xxx devices?

Thank you!

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  • A timeslot is a period of time from 100 µs to 128 s in which the SoftDevice will render full control over the radio and other restricted peripherals to the user. This means that you can use the radio while still maintaining a BLE connection or do tasks that you need to do uninterrupted by radio activity.

    The SWIx refers to the six software interrupts available from the SWI pool, SWI0 to SWI5. The SoftDevice uses SWI2-5. If you are using the SoftDevice you can use SWI0 for yourself, and you can also use SWI1 if you aren't using radio notifications. If you aren't using the SoftDevice then you can use all 6 of them.

    Here is the SoftDevice NVIC API. The NVIC registers are not described in the Reference Manual, since they are generic and similar for all Cortex M0. You can therefore refer to ARM's documentation on them.

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  • A timeslot is a period of time from 100 µs to 128 s in which the SoftDevice will render full control over the radio and other restricted peripherals to the user. This means that you can use the radio while still maintaining a BLE connection or do tasks that you need to do uninterrupted by radio activity.

    The SWIx refers to the six software interrupts available from the SWI pool, SWI0 to SWI5. The SoftDevice uses SWI2-5. If you are using the SoftDevice you can use SWI0 for yourself, and you can also use SWI1 if you aren't using radio notifications. If you aren't using the SoftDevice then you can use all 6 of them.

    Here is the SoftDevice NVIC API. The NVIC registers are not described in the Reference Manual, since they are generic and similar for all Cortex M0. You can therefore refer to ARM's documentation on them.

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