How to identifier nRF51 SoC chip?

[wen jin zhang]

I try use the FICR information to identifier nRF51. but found some interesting staff when i read 0x10000000 first 16 bytes by SWD memory read. when I power on read. it return all 0x00. but i restart SWD debuger read again. it will return 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

and CONFIGID also same.

do FICR be RTL? why could be changed, ? is there has fixed area can be used as identifier?

[Susheel Nuguru]

Not sure why you were reading 0x00's but the FICR is permanent device and calibration data tuned for each chip, it will/should not change.

[wen jin zhang]

I using SWD to read FICR. first use these code setup and enter SWD debug mode.

    swd_init();

    //add Reset Pin
    swd_set_target_reset(1);
    os_dly_wait(1);
    swd_set_target_reset(0);
    //need wait 500us
    for( i = 0; i < 1200; i++) {}

   //init SWD sequence and get IDcode
    if (!swd_reset()) {
        return Target_UNKNOWN;
    }
    if (!swd_switch(0xE79E)) {
        return Target_UNKNOWN;
    }
    if (!swd_reset()) {
        return Target_UNKNOWN;
    }
    if (!swd_read_idcode(&tmpid)) {
        return Target_UNKNOWN;
    }

    if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR)) {
        return Target_UNKNOWN;
    }

    // Ensure CTRL/STAT register selected in DPBANKSEL
    if (!swd_write_dp(DP_SELECT, 0)) {
        return Target_UNKNOWN;
    }

    // Power up
    if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
        return Target_UNKNOWN;
    }

    do {
        if (!swd_read_dp(DP_CTRL_STAT, &tmp)) {
            return Target_UNKNOWN;
        }
    } while ((tmp & (CDBGPWRUPACK | CSYSPWRUPACK)) != (CDBGPWRUPACK | CSYSPWRUPACK));

then read FICR use swd_read_memory().

[Susheel Nuguru]

Hi vjzhang,

I am not sure how you are entering debug mode. I can see your function calls but i cannot see what they are doing. The quote from specs says that you need the below

Debug interface mode is initiated by clocking one clock cycle on SWDCLK with SWDIO=1. Due to delays caused by starting up the DAP's power domain, a minimum of 150 clock cycles must be clocked at a speed of minimum 125 kHz on SWDCLK with SWDIO=1 to guarantee that the DAP is able to capture a minimum of 50 clock cycles.

I do not see where you are doing this.

[wen jin zhang]

what is right sequence access the FICR? i check again. use swd_read_word(0x10000000, &tmp) function. and it return OK. but tmp value is 0x00000000 when power on. then no power off. then entry debug mode and read again. the tmp will be 0x55AA55AA.

The SWD init sequence is ok!

[David García Polo]

Reading FICR area is the same as reading any flash on the device. Flash should be available when the SWD resources are available. Are you certain you actually read 0x0 and you do not get anything back in your SWD operation and then it is interpreted as a 0x0 instead? also, FICR is actually flash, so it does not change value.