I have following code fragment to enter nRF52 into power-off mode. There is s132 softdevice 3.0.0 running and my SDK is 12.0.0:
int32_t ret = sd_power_system_off();
// get here if softdevice is not running
debuglnf("sd_power_system_off() == %d", ret);
NRF_POWER->TASKS_LOWPWR = 1;
NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
But what really happens, is that by code continues running with a return value 8198 from the sd_power_system_off() call. I guess it might be NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN.
Furthermode, although there are those direct register pokings to enter system off if sd_power_system_off() fails, what really happens is that the system continues running. But not like normally! According to my RTT debug prints it looks like it runs VERY SLOWLY, maybe around one tenth of normal speed. It might also be that my timers stop running entirely, since timer based activities are stopped.
What the heck is going on there? I would need help to get the system into true power-off state and would really appreciate any hints.
I am pretty sure you are seeing this in debugger. In debug mode system off does not work. Instead, emulated system off is used which does not go to deep sleep and the CPU continues to run. But the wakeup source will reset the chip in both emulated system off and normal system off. We added this feature for debugging. One way to verify that your system off feature is working in debugger is to trigger the wakeup source and see if it has reset the chip.
Also it is important to have a while(1); after the triggering the system off. Else in debug mode, since the CPU continues to run, it will cause some hardware fault because it will start executing something which it is not supposed to.
Please read product specifications for more info at infocenter.
did you get to check if this was the case for you Jarmo?
It might be the case. I am using RTT to see debug printings, so does that mean the system is in debug mode and thus emulates system off?
No, it is in debug mode if you started debugger or explicitly made chip to go to debug mode by controlling the SWD lines after the chip went to SystemOFF
I believe using the RTT terminal from a PC will also put the chip in debug mode!