Is it possible by any chance to have the SPIS working on an nRF52 without using the CS pin?
Is it possible by any chance to have the SPIS working on an nRF52 without using the CS pin?
Hi,
As described in the product specification of nRF52832, the SPI Slave interface use two memory pointers, RXD.PTR and TXD.PTR, to point to memory buffers. As these are located in RAM, they can be accessed by both CPU and the SPIS interface. A semaphore is used to aquire access to these registers, to avoid interfering with CPU activity. The semaphore is tried aquired on CSN pin low drive, and released when CSN goes high again. It is therefore not possible to use SPIS without the CSN pin, as this signal is needed to know when to aquire the semaphore.
Best regards,
Jørgen
No, the CS is connected to the semaphore aquire request, and this have to be relased between each SPI transfer. By tying CS permanently low, the semaphore will never get released and this will prevent CPU from accessing the buffers.
No, the CS is connected to the semaphore aquire request, and this have to be relased between each SPI transfer. By tying CS permanently low, the semaphore will never get released and this will prevent CPU from accessing the buffers.