Is it possible by any chance to have the SPIS working on an nRF52 without using the CS pin?
Is it possible by any chance to have the SPIS working on an nRF52 without using the CS pin?
Hi,
As described in the product specification of nRF52832, the SPI Slave interface use two memory pointers, RXD.PTR and TXD.PTR, to point to memory buffers. As these are located in RAM, they can be accessed by both CPU and the SPIS interface. A semaphore is used to aquire access to these registers, to avoid interfering with CPU activity. The semaphore is tried aquired on CSN pin low drive, and released when CSN goes high again. It is therefore not possible to use SPIS without the CSN pin, as this signal is needed to know when to aquire the semaphore.
Best regards,
Jørgen
Yes, but it is still implemented in such a way that the CPU will aquire the semaphore when accessing the registers. If CSN is set low, the CPU will not aquire the semaphore until a rising edge of CSN is detected. The semaphore must also be reaquired by the SPI slave interface again for each transfer. I guess it could be possible to ignore this semaphore safety mechanism by accessing the registers directly, but then you will have no control over the validity of the data in the registers. This is not something that is supported by our drivers.
Yes, but it is still implemented in such a way that the CPU will aquire the semaphore when accessing the registers. If CSN is set low, the CPU will not aquire the semaphore until a rising edge of CSN is detected. The semaphore must also be reaquired by the SPI slave interface again for each transfer. I guess it could be possible to ignore this semaphore safety mechanism by accessing the registers directly, but then you will have no control over the validity of the data in the registers. This is not something that is supported by our drivers.