Is it possible by any chance to have the SPIS working on an nRF52 without using the CS pin?
Is it possible by any chance to have the SPIS working on an nRF52 without using the CS pin?
Hi,
As described in the product specification of nRF52832, the SPI Slave interface use two memory pointers, RXD.PTR and TXD.PTR, to point to memory buffers. As these are located in RAM, they can be accessed by both CPU and the SPIS interface. A semaphore is used to aquire access to these registers, to avoid interfering with CPU activity. The semaphore is tried aquired on CSN pin low drive, and released when CSN goes high again. It is therefore not possible to use SPIS without the CSN pin, as this signal is needed to know when to aquire the semaphore.
Best regards,
Jørgen
From my understanding the semaphore for the CPU is only a method to know whether the SPIS is writing into those buffers, but it doesn't prevent the CPU access.
"The semaphore mechanism does not, at any time, prevent the CPU from performing read or write access to the RXD.PTR register, the TXD.PTR registers, or the RAM that these pointers are pointing to. The semaphore is only telling when these can be updated by the CPU so that safe sharing is achieved."
From my understanding the semaphore for the CPU is only a method to know whether the SPIS is writing into those buffers, but it doesn't prevent the CPU access.
"The semaphore mechanism does not, at any time, prevent the CPU from performing read or write access to the RXD.PTR register, the TXD.PTR registers, or the RAM that these pointers are pointing to. The semaphore is only telling when these can be updated by the CPU so that safe sharing is achieved."
