What is the right configuration of registers for NRF24L01P (TX mode and RX mode)

[Mohamed Akaarir]

After i test a lot of possible configurations for nrf24L01+ based on the documentation, i didn't come to the right setup for all the nRf24L01+ registers to send data from a module as an emitter and to receive as a receiver. here is the configurations i made for the initiation ( Transmitter)

config_transmiter();           // set as transmiter and power up
setRADDR();                    // address for pipe 1 
setTADDR();                    // same for receiver of pipe 0
rf_setup() ;
payload_size(8);               // 5 bytes
setRF_CH();                    // 2.431GHz
flushTX();                     // clear any data in TX FIFO
en_RXADDR(0x3F);
auto_ack(0x3F); 

address RX : 0x65646f4e32 address TX : 0x65646f4e31

( Receiver)

config_receiver();           // set as transmiter and power up
setSETUPAW();
setRADDR();                    // address for pipe 0 
setTADDR();                    // same for trasmiter
rf_setup() ;
payload_size(8);               // 5 bytes
setRF_CH();                    // 2.431GHz
flushRX();                     // clear any data in RX FIFO
en_RXADDR(0x3F);
auto_ack(0x3F);                // enable auto acknowledgment

address RX : 0x65646f4e31 address TX : 0x65646f4e31

[ovrebekk]

Hi Mohamed

When using the auto ACK (ESB) features of the nRF24L01+ you want to make sure that the TX and Pipe 0 address is the same on the PTX side. The reason for this is that the PTX uses pipe 0 to receive the acknowledgement sent by the PRX.

Also, I can only see setSETUPAW(); referenced on the RX side. If you have a different address length on the TX and RX side then communication will fail.

If you still have issues after checking these things, then it would help if you could write down the state of the configuration registers on both sides. Then I can look them over and see if I spot any more issues.

Best regards
Torbjørn

[ovrebekk]

Hi Mohamed

I can't really spot any issues with your code.

Can you double check that the SPI is configured correctly, in terms of bit order, clock polarity and so forth?

For reference I have attached a screenshot of how it should look like when you set the PRIM_RX and PWR_UP bits by writing 0x0B to the CONFIG register. If you are able to scope the lines you can double check that it looks the same.