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Definitive information on GPREGRET register

Hello,

The Nordic documentation is pretty thin on what I can expect out of this 8-bit storage area. Perhaps some specific questions are in order:

  1. How is it implemented? The fact that the sd_power_gpregret_clr() call specifies the bits to clear implies some form of flash.

  2. Are the contents retained if I perform a bulk flash erase of the part?

  3. Are the contents retained if I enter sd_power_system_off()?

  4. the nRF51 Series Reference Manual states that its reset value is 0x00 - does that mean an external reset event over the SWD interface will clear it to zero?

  5. Replies here suggest it is unavailable with the S210 SoftDevice. Is that still the case?

Thank you all very much and I apologize if these seem simplistic but I'd like to see all of this information in one area.

Dan Danknick

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  • Hi Dan,

    I like your thinking, It's smart to have this information centered in one thread.

    1. It's a RAM mapped retained register which will lose it's content after power-cycle, however it keeps its content after a wakeup from SYSTEMOFF mode. It's implemented like that in the softdevice so that you can easily use the individual bits.

    2. Then it's to be considered gone.

    3. Yes, it is.

    4. An external reset will clear it.

    5. It's added from S210 v3.0.0, quote from releasenotes:  SOC API SVC Additions o sd_power_gpregret_set / sd_power_gpregret_clr / sd_power_gpregret_get  APIs added for access to general purpose retention register

    It's defined in nrf_soc.h.

    Best regards Håkon

  • It's smart to have this information centered in one thread.

    Would be smarter to have it in the actual documentation!


    It's implemented like that in the softdevice

    You mean as a bit set/clear mask?

    Does this mean that the register hardware itself does not work that way? ie, the register hardware itself is just a straight byte read/write ?

    It's also important to note that, although the SD APIs use 32-bit values, both GPREGRET and GPREGRET2 (nRF52832) are only 8 bits!

    It would be helpful if the SD documentation noted this specifically.

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  • It's smart to have this information centered in one thread.

    Would be smarter to have it in the actual documentation!


    It's implemented like that in the softdevice

    You mean as a bit set/clear mask?

    Does this mean that the register hardware itself does not work that way? ie, the register hardware itself is just a straight byte read/write ?

    It's also important to note that, although the SD APIs use 32-bit values, both GPREGRET and GPREGRET2 (nRF52832) are only 8 bits!

    It would be helpful if the SD documentation noted this specifically.

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