Hello,
SPIS is adding a 350uA from 80uA baseline running current. I would like some tips and advise on improving this. Thanks!!!
The baseline operation consists of:
Wakeup every 2ms by SPIM transfer done Interrupt, 10 byte SPIM xfer with PPI triggered by GPIOTE port event, and then some processing (this gives about 50us SPIM + 5us CPU wake time per 2ms), note that, all GPIOTE interrupts are masked off, so that the CPU wakes up to SPIM interrupts after the Xfer is done and does not respond to GPIOTE event, this baseline is taking about 80uA without the SPIS.
The bench setup is:
Devkit 10040 with QFAAB0 ( I think this is rev 1 IC). Keil with default up to date packs. RTT disabled for current drain observations. Proper pull down and pull ups and cut short bridges are in place for low current through configured IO pins.
The SPIS function is being added into this dev work, it is operating, the drivers used for setting this up is outlined below:
nrf_drv_spis_config_t spisConfig = NRF_DRV_SPIS_DEFAULT_CONFIG(SYS_SPIS_INSTANCE);
spisConfig.mode = NRF_DRV_SPIS_MODE_0;
spisConfig.orc = 0x00;
spisConfig.csn_pin = SYS_SPIS_NCS_DI_PIN;
nrf_drv_spis_init(pSysSpis, &spisConfig, sysSpisEventHandler);
Configuration file with SPIS enabled, pins assigned and EasyDMA enabled.
It seems that everytime for a SPIS xfer to run properly, the nrf_drv_spis_buffers_set() call is needed for a setup.
I am wondering whether there are other ways to use the SPIS to make it more efficient? Especially minimize the 350uA added current drain.
Thanks again
FI
