GPIO state unpredictable when Vdd is below 1.6V URGENT!!!

[TY]

Hi dev team, in my design I am using the nRF52832.

On the GPIOs (P0.14,P0.15) I've connected a Darlington Array (ST ULN2001).

My circuit is living of a super cap and therefore the voltage ramp during the initial charge is very slow. On some boards I have the problem that the mentioned pins are in a weird state (around 0.6V) till Vdd reaches 1.7V then in the first lines of code I set those pins to LOW. However, sometimes those pins just start driving the Darlington Transistors and short my bus which also provides my power. I can observe these behavior also when the flash is erased.

According to the datasheet the pins should be floating and the internal pull-downs of the resistors should ensure that the Darlington Transistors are off.

I am desperate because these HW revision supposed to go into production NOW. Any suggetion is appreciated. Cheers Timur

[Krunal Desai]

Isn't <1.7V undefined operating region for the part? I'd argue that this is exactly what pull-down resistors are for -- enforcing the state of the system before a device comes out of reset / can assert pin states. The internal GPIO cells may simply not function below a certain VDD where the transistor Vt can't be met.

10K-100K PDs would fix this I think -- 330uA "wasted" with a 10K, 33 with a 100K assuming 3.3V target VDD. But I would treat those pins as 100% floating nets until the nRF can operate and set output levels.

An alternate would be finding a part with an EN pin or similar, where you can pay the penalty for a pull-down only once instead of per channel.

[Daniel Wang]

Default pin state is: Input pin, No Pull, Disconnected input buffer, S0S1 drive, Sense Disabled

[Roger Clark]

Have you considered putting a diode between the GPIO and the Darlington input?

[TY]

Why a diode? Do you think the threshold voltage would avoid the Darlington Array to turn on?