Offset in SAADC samples with Easy DMA and BLE

[Velitsu]

I have a nrf52 application that samples four saadc channels at 1kHZ. That is: Map four pins to ADC input and let Easy DMA take care of the sampling so that the data is processed ten times a second (100 * 4 samples). This works pretty well, except...

When I enable the BLE connection, the data is shifted in the buffer. Without BLE enabled, the data layout in the memory is as following {{1,2,3,4}, {1,2,3,4}, ...}. But, when BLE is activated, the memory layout is: {{4,1,2,3}, {4,1,2,3}, ...} I really don't know what causes the difference. I have no way to check if the data is shifted, or did the samples just swap places. I wonder if the softdevice blocks some of the samples that would cause the problem.

The saadc implementation is double buffered, like in "saadc_sample_from_two_pins - scan mode" here

The BLE implementation is based on ble_app_hrs_freertos in SDK 12.1.0. That is also the SDK version I'm using.

Any help would be appreciated.

[Jørgen Holmefjord]

Hi,

There have actually been some progress with this issue. The reason why this swap/shift in the buffer occurs, is related to how samples are triggered, and how events are handled.

The EasyDMA chapter in the SAADC documentation show the order of tasks and events for proper operation.

The problem arise when the SAADC is configured in continuous mode using PPI to trigger the SAMPLE task at a regular interval, while the END event and START task is handled by CPU interrupt. When the SAMPLE task is triggered, each channel is sampled and written to RAM with DMA as fast as possible. When the buffer have been filled, the DMA transfer will be delayed until the START task have been triggered. You are triggering the START task in the interrupt handler after receiving the END event. If you receive the END event when IRQ is disabled or an interrupt with higher priority is executing, the triggering of the START task can get delayed until after the SAMPLE task have been triggered using PPI. Triggering of the SAMPLE task will generate a DMA transfer request, but this request will not be acknowledged until the START task have been triggered. The scan cycle of the SAADC will however expect the DMA transfer to finish, and will sample next channel. When the START task is triggered, the pending DMA transfer will be executed, but the transferred sample will correcpond to the latest sampled channel. Samples from previous channels will have been lost.

There are two possible solutions to this problem:

1. Use PPI to trigger START task on an END event. This will avoid the delayed triggering og the START task due to a queued interrupt generated by the END event, but in the case of high sample frequency and long delays, it can cause your buffer to be overwritten before you are able to process the buffer. In case of using this solution, it is neccessary to use double buffering and large enough buffers to avoid data loss.
2. Trigger sampling from CPU interrupt. If the SAMPLE task is triggered from an interrupt with lower priority than the SAADC IRQ handler, the START task will always be triggered between an END event and a new SAMPLE task. This solution will make the sampling vary a bit in time, as higher priority tasks can cause the triggering of SAMPLE task to be delayed.

This is a typical case of hard real-time requirements, that cannnot be guaranteed with a task/event based system. Since many users are experiencing this issue, we will try to update the documentation to make this requirement more visible.

Best regards,

Jørgen

[Mike Melbot]

I've just hit a similar issue.
I'm using the nRF52810. I'm using the driver to sample 4 channels (AIN0 through AIN3) at 120 Hz to a 32-sample long double buffer using TIMER1 as a hardware timer. It's very important to sample at precise intervals, so I can't trigger the SAMPLE task via software.

My PPI setup used to be:
TIMER1->EVENTS_COMPARE[0] ==== (short) ====> TIMER1->TASKS_CLEAR
TIMER1->EVENTS_COMPARE[0] ==============> SAADC->TASKS_SAMPLE

(TIMER1 is started on boot via software after the SAADC is initialized)

It worked fine apparently. however, when hitting a breakpoint or on some BLE events, the channel order gets swapped from 1, 2, 3, 4 to 2, 3, 4, 1.

Then I stumbled upon this thread and changed the PPI setup as follows:
TIMER1->EVENTS_COMPARE[0] ==== (short) ====> TIMER1->TASKS_CLEAR
TIMER1->EVENTS_COMPARE[0] ==============> SAADC->TASKS_SAMPLE

SAADC->EVENTS_END ===============> TIMER1->TASKS_STOP

SAADC->EVENTS_STARTED ===========> TIMER1->TASKS_START

(TIMER1 is not started via software on boot)

This way I prevent the SAMPLE task to be triggered before the driver swaps the buffers.

My questions:
1.- Can you foresee any further issues with this fix?.
2.- I don't care about occasional glitches in the sampling interval due to the CPU being too busy to swap the buffers and trigger the SAADC START task on time when the current buffer runs out as long as they are few and sparse. Is there potential for severe or frequent glitches with this approach, or can you suggest an alternative workaround to avoid the glitches at all?

Thanks for your assistance and take care!!

[Jørgen Holmefjord]

1. This should prevent you from triggering the SAMPLE task while the SAADC is not started, so I believe this solution should work.

2. The frequency and length of the glitches will depend on the BLE activity and other higher priority events. But this solution will shift the sampling point around in time when you start/stop the timer, is this not a problem as long as the time between the samples is constant?