Timer Drift Clarification

[jpelo]

Working with nRF52832 and SD132-v2.0.1

Using external 32.768kHz xtal in addition to 32MHz xtal.

I realize there are a lot of posts about timers, but I didn't find any posts that answered my question(s).

I'm using a timer running at 1MHz to generate interrupt every 10ms (range from ms to minutes). Using short to clear the timer on CC match. I'm ok with interrupt latency to handle/process interrupt. I am seeing a drift between the RTC and the Timer (~1ms every ~11s).

Is is accurate to assume this drift can be attribute to (1) time to clear timer per manual "After the TIMER is started, the CLEAR task, COUNT task and the STOP task will guarantee to take effect within one clock cycle of the PCLK16M." (so worse case delay of 1/16M per int?) and (2) tolerances diffs between 32k and 32M xtals? The maths indicate this is possible but unsure if I'm missing something.

Am I correct that shorts don't require CPU so there isn't additional overhead for the clear? regardless of cpu sleep state?

I'm also curious if there is a way to calibrate the 32MhHz or the 16M peripheral clock against the 32k xtal?

[jpelo]

thanks for the response Sigurd. yeah, i'm calculating the same (~90ppm) which is why i asked the question. i'm measuring my drift based on rtc ticks vs us timer ticks (time stamp from rtc). 32k is 20ppm. unfortunately im using a module so dont have direct access to the 32M inside, but assume its 40ppm or less. considering the latency of up to 1/16M and the 2 xtal tolerances, in absence of error this is possible?