Hi
To write the some state of the device, I write two bits into the NVM memory. Thus, we get 16 write cycles to one address without erasing. I did this based on the optimization of erase / write cycles. A few weeks of testing the device works without complaints. On the phrase in the specification "Number of times an address can be written between erase cycles - 2" unfortunately I did not pay attention. :( How critical is this parameter in practice? In 52xxx, rewriting is allowed 181 times. Should I rewrite the algorithm or is this parameter given with a margin of safety? Thank you.
