I do have an I2S audio application for the nRF52; it is an audio recording peripheral application using an Invenvense MEMS microphone. It was a bit trick to pull off though...
Almost all 24-bit I2S microphones output 24 data bits per stereo channel but require 32 SCK pulses per channel to function properly. So, the stereo I2S frame needs to be 64 SCK pulses wide. Like everyone else, I was attempting to collect audio data from a modern 24-bit I2S MEMS microphone and ran into the hard-coded limitation of 48 SCK pulses per stereo I2S frame in I2S master mode. The I2S frame will never be 64 SCK pulses wide In master mode but in I2S slave mode the nRF52 will properly decode the 24 data bits per channel even if the the frame is 64 SCK pulses wide. After reading the I2S protocol spec, It dawned on me that there really is precious little difference between I2S master and slave modes... Just where the LRCK and SCK pulses come from.
My solution was to augment the PWM library to set the PWM carrier period directly in 16MHz ticks, not milliseconds. So I use two PWM channels; one to generate SCK and the other to generate LRCK and connect the PWM outputs to the I2S SCK and LRCK pins. I set the LRCK PWM channel period to be 64X that of the SCK PWM chanel period. So I'm making synthetic SCK and LRCK clock signals....
I have a functioning peripheral application for SDK 13.0.0 and the pca10040 DK board located here:
I do have an I2S audio application for the nRF52; it is an audio recording peripheral application using an Invenvense MEMS microphone. It was a bit trick to pull off though...
Almost all 24-bit I2S microphones output 24 data bits per stereo channel but require 32 SCK pulses per channel to function properly. So, the stereo I2S frame needs to be 64 SCK pulses wide. Like everyone else, I was attempting to collect audio data from a modern 24-bit I2S MEMS microphone and ran into the hard-coded limitation of 48 SCK pulses per stereo I2S frame in I2S master mode. The I2S frame will never be 64 SCK pulses wide In master mode but in I2S slave mode the nRF52 will properly decode the 24 data bits per channel even if the the frame is 64 SCK pulses wide. After reading the I2S protocol spec, It dawned on me that there really is precious little difference between I2S master and slave modes... Just where the LRCK and SCK pulses come from.
My solution was to augment the PWM library to set the PWM carrier period directly in 16MHz ticks, not milliseconds. So I use two PWM channels; one to generate SCK and the other to generate LRCK and connect the PWM outputs to the I2S SCK and LRCK pins. I set the LRCK PWM channel period to be 64X that of the SCK PWM chanel period. So I'm making synthetic SCK and LRCK clock signals....
I have a functioning peripheral application for SDK 13.0.0 and the pca10040 DK board located here:
