I2S timing

[Erblin]

Hi,

I am currently testing a DAC with I2S input supplied by the nRF52832. But unfortunately no signal is coming out from the DAC, furthermore when reading the error registers on the DAC through i2c I get a clock error which indicates that the clock ratio is not valid. I have discussed this with Texas Instruments audio forum, but they tell me that the clocks are valid and they point out to rather check if the I2S timing from the nRF is correct. (link to Texas forum)

Is the I2S module on the nRF52832 set to follow the I2S timing specifications?(shown in this link) I wasn't able to measure those parameters, because my scope wasn't precise enough :(

The DAC which I am using is the TAS5760L, link to datasheet.

-Erblin

[Jørn]

Hello Erblin

With the settings you mention in your post at Texas Instruments you should have a LRCLK, and SCLK error of approximately 3.1% which is within the 10% specified in the I2S Specification.

Both of these are also within the 4% Alex Bhandari-Young at TI's forum had found for a similar product.

In the TAS5760L product specification, legal clock ratios for SCLK/LRCLK are 32, 48 and 64. With your settings, this ratio is 32. Legal clock ratios for MCLK/LRCLK is 64, 128, 192, 256, 384 and 512. With your settings, this ratio is 64.

As of yet I have not found any specific reason the nRF52832 should not be compatible with the TAS5760L, as all values seem to meet the requirements. I see Alex Bhandari-Young with TI has requested more information on clock tolerances, it will be interesting to see what he finds.

I have found a post on Texas Instruments' support forum, which seems similar to your issue e2e.ti.com/.../1797838 Please have a look and see if that can be of help.

Best regards

Jørn Frøysa

[Erblin]

The TWI pins are the default arduino TWI pins (P27&P26), while the I2S uses 3, 4, 28 and 29. So pins 26 to 29 are positioned relatively closed to each other. I can just exchange 3 and 4 with 27 and 26 to make them further apart. The TWI was set to 400 KHz, there is no problem for changing it to 100 KHz if necessary.

But is the GPIO's rise time within specification when increasing the pins drive strength?