Does hardware control SPIS MISO Pin?

I've run into some interesting behaviour in my code and wanted to see if anyone can clarify for me. It seems as though the SPIS module doesn't set the MISO pin as high impedance when the CSN pin is deassertted as the documentation on the infocenter suggests.

From the SPIS section of the infocenter: "The MISO line is set in high impedance as long as the SPI slave is not selected with CSN."

What appears more correct is that the SPIS module will put the MISO pin state back to whatever settings are in the GPIO register when the CSN pin is deasserted.

I encountered this behaviour because I had called "nrf_drv_spis_init(...)" from the SDK - which sets the MISO pin as an input. Immediately after that in my code I set the direction to output and high drive strength - expecting that the MISO line would be 'set in high impedance as long as the SPI slave is not selected with CSN' as the infocenter stated. What I saw instead is that the MISO pin actually got driven from that point forward, whether or not CSN was asserted - it never got set to high impedance.

I would suggest that the wording in the infocenter documentation be changed to reflect the real behaviour of the pin, because as it is now it appears misleading. Or perhaps this is errata and the MISO pin was actually supposed to be forced to be an input when CSN was deasseted. Which is it?