ADC with internal pull up

[Jimmie Johansson]

This is for the nRF51822.

I have done some tests where I configure a pin as input with pull up enabled and then reconfigure the pin for an adc measurement with 1/3 prescaler with band gap reference.

It looks like the pull up is enabled when the adc measurement is done (which is very helpful for my use case), but I can't find information about this in the datasheet and previous questions on devzone have comments that indicate that it is not enabled in adc mode.

Has anyone else seen this behaviour and can I trust that it works the same in different revisions of the silicon?

[testy]

I can confirm exactly the same behaviour: nRF51422 QFAA F0 (3rd rev). Pull-up stays enabled and causes (un)desired voltage offset during ADC operation.

[Jørn]

Hello Jimmie Johansson

I have looked into this and you are correct that if the GPIO pull-up and pull-down resistors have been enabled, they are still connected when the ADC samples unless explicitly disabled before that. From what I have found this is the case for both the nRF51 and nRF52 series. It is not clearly stated in the documentation, and this has been reported.

To ensure correct behavior you will need to take care and disable the pull-up and down resistors before starting the ADC sampling.

I believe this will also apply when using the comparator.

Best regards

Jørn Frøysa