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Memory warnings in SES v3.24

So I thought I would upgrade one of my projects to SDK13 and try out SES 3.24 at the same time. I thought I would start by getting the ble_app_uart_pca10040_s132 project to work first.

Alarmingly I am getting a strange warning on running the project as seen below.image description.

My MemoryMap.xml is <!DOCTYPE Board_Memory_Definition_File> <root name="nRF52832_xxAA"> <MemorySegment name="FLASH" start="0x1f000" size="0x61000" access="ReadOnly" /> <MemorySegment name="SRAM" start="0x200025f8" size="0xda08" access="Read/Write" /> </root>

So SES is suggesting RAM needs to be adjusted to something it (or more specifically SRAM) already is.

Seeing this this makes me nervous that something isn't set up correctly that will come back to bite later.

This is nRF52832 QFAA s132 SD4.0.2.

Does anyone have any ideas here?

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  • SES isn't suggesting anything, this has nothing to do with the IDE at all. What you're seeing is the warnings built into the SDK which check RAM set against RAM actually required on enable and print out any differences.

    So go put a debug in there and find out what you're actually sending in, what it's actually returning and then work out what SES setting needs to be changed. It's in the softdevice enable code somewhere, should take all of 10 seconds to find.

  • I'm sure it's picking up the memory map, 200525f8 is just the start of SRAM (and it seems wrong because the start of RAM is 20000000). The actual place used to put the code is usually passed in via a macro (as you have now done).

    The memory map defines the layout of the chip to build the linker file and should represent the actual layout of the chip, other macros control where you actually place the start of sections.

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  • I'm sure it's picking up the memory map, 200525f8 is just the start of SRAM (and it seems wrong because the start of RAM is 20000000). The actual place used to put the code is usually passed in via a macro (as you have now done).

    The memory map defines the layout of the chip to build the linker file and should represent the actual layout of the chip, other macros control where you actually place the start of sections.

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